This invention relates to a MOS field-effect transistor with sidewall spacers at the gate electrode sides, and more particularly to such a type of field effect transistor formed in a lightly doped drain (LDD) structure (referred to as an LDD transistor hereinafter).
A LDD transistor in the prior art comprises source/drain layers of a lower impurity concentration (referred to as LIC hereinafter) on the surface of a semiconductor substrate underneath the sidewall spacers of insulating material and source/drain layers of a higher impurity concentration (referred to as HIC hereinafter) at respective sides of LIC source/drain layers. The surfaces of the HIC source/drain layers are at respective outer sides of the sidewall spacers and connected to source/drain electrodes, respectively. The reason why the LIC drain layer is located underneath the sidewall spacer is to prevent the undesirable effect of hot carriers. Without LIC drain layers, then electric field concentration would occur in the vicinity of the drain just beneath the gate electrode, thereby generating hot carriers which in turn would be injected into the gate-insulating layer, leading to varying threshold voltage of the transistor. The formation of the LIC drain layer causes the peak electric field to relocate underneath the sidewall spacer, resulting in suppressing the injection of hot carriers into the gate-insulating layer and in turn preventing the threshold voltage of the LDD transistor voltage from varying.
In a LDD transistor where the peak field effect is found underneath the sidewall spacer, hot carriers are injected into the sidewall spacer This produces an undesirable phenomenon that degradation of the transistor noted as lowering the transconductance (gm) of the transistor with the lapse of time, occurs in the initial stage, not gradually but sharply. In an effort to prevent this, a slight increase in impurity concentration in the LIC drain layer can cause the peak electrid field to locate just underneath the gate electrode, but this results in inducing the above-mentioned varying threshold voltage.
The p-channel MOS transistor is less affected by hot carriers due to electric field concentration than is the n-channel MOS transistor. In conventional CMOS integrated circuits (referred to as ICs) therefore LDD structure was used only for the n-channel MOS transistor and not done for p-channel MOS transistors. Application of LDD structure to the p-channel MOS transistor as well, though advantageous from the viewpoint of improving the reliability, is difficult because the conventional CMOS ICs require additional photolithographic processing step for this.